The present invention relates generally to testing of integrated circuits, and more particularly, to scan testing of integrated circuits.
Transition fault testing is an important test performed during the design phase of an integrated circuit to identify and locate signal transition faults. The test, also known as an at-speed test, is widely carried out at rated clock speed to test the response of an integrated circuit. At-speed tests can be performed as scan tests that involve selecting a scan path in the integrated circuit for testing. During a scan test, an input signal is provided to a pin in the scan path. The signal propagates through the scan path and a value of the signal is read at a destination pin in the scan path. The scan out value is examined to determine if the scan-in and scan-out pins are properly connected.
For scan testing, the integrated circuit is divided into a plurality of on-chip logic modules. Each on-chip module is further segmented into scan chains or paths. A scan path refers to a chain of digital logic elements (e.g., flip-flops, latches, and data registers) within an on-chip module. An external automatic test pattern generator (ATPG) tool is connected to the integrated circuit, which generates and ports test patterns to the integrated circuit. The ATPG tool specifies one of the on-chip modules for scan testing and tests each scan path therein (also referred to as module level scan testing). After each on-chip module is tested independently, the ATPG tool regenerates test patterns for testing scan paths within one or more of the on-chip modules together (also referred to as chip level scan testing).
Chip level scan testing is a tedious and time consuming task as the ATPG tool requires a considerable amount of time for generating new test patterns. For example, chip level scan testing of a system-on-chip (SoC) that includes about 500 million transistors requires more than 1000 processors to generate test patterns and around nine months to complete testing and verification. A typical design cycle of a SoC of the size described above is about two to three months. Therefore, completing the entire scan testing (module and chip level scan testing) within the span of the design cycle is often impossible and leads to design delays. Moreover, any failure during chip level scan testing requires about seven additional days for the ATPG tool to regenerate corresponding test patterns, which further adds to the test time. Thus, existing test tools and techniques introduce a significant delay in time-to-market (TTM) of an integrated circuit.
Therefore, there is a need for a way to reduce the time needed to generate scan test patterns in order to reduce the overall time required for scan testing an integrated circuit and that overcomes the above-mentioned limitations of existing scan test solutions.